An SR latch is one of the most fundamental memory elements in digital electronics. It stores a single bit of information and forms the conceptual basis for flip-flops, registers, counters, and many sequential logic circuits. Although simple, the SR latch must be understood carefully because its behavior depends not only on input values, but also on prior state and timing.
TLDR: An SR latch is a basic 1-bit memory circuit with two main inputs: S for set and R for reset. For example, in a small control circuit, pressing a “start” button can set the latch to keep a motor enabled until a “stop” button resets it. In a typical digital lab exercise, students can verify all four input cases in under 10 minutes, but about 25% of beginner mistakes come from misunderstanding the invalid input condition.
What Is an SR Latch?
An SR latch, also called a Set Reset latch, is a bistable circuit. Bistable means it has two stable output states: logic 0 and logic 1. Once placed into one of these states, the latch remains there until a valid input forces it to change.
The circuit has two outputs, usually labeled Q and Q̅. In normal operation, Q̅ is the complement of Q. If Q is 1, Q̅ is 0; if Q is 0, Q̅ is 1. This complementary relationship is essential because it indicates that the latch is storing a valid binary value.
There are two common implementations:
- NOR based SR latch: Active high inputs. A logic 1 on S sets the latch, and a logic 1 on R resets it.
- NAND based SR latch: Active low inputs. A logic 0 on S̅ sets the latch, and a logic 0 on R̅ resets it.
This article focuses first on the NOR based SR latch, since it is often the easiest version to understand conceptually.
How a NOR Based SR Latch Works
A NOR based SR latch is built from two cross coupled NOR gates. The output of each NOR gate feeds into one input of the other gate. This feedback is what allows the circuit to remember its previous state.
The inputs are:
- S: Set input
- R: Reset input
The outputs are:
- Q: Stored output bit
- Q̅: Complement of Q
When S = 1 and R = 0, the latch is set, so Q becomes 1. When S = 0 and R = 1, the latch is reset, so Q becomes 0. When both inputs are 0, the latch holds its previous state.
NOR SR Latch Truth Table
| S | R | Q Next | Q̅ Next | Operation |
|---|---|---|---|---|
| 0 | 0 | Q Previous | Q̅ Previous | Hold |
| 1 | 0 | 1 | 0 | Set |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 1 | 0 | 0 | Invalid |
The final row is the most important warning. In a NOR SR latch, S = 1 and R = 1 force both outputs to 0. This violates the expected complementary relationship between Q and Q̅. When both inputs return to 0, the final state can become unpredictable due to small propagation delay differences between the gates.
Understanding the Hold Condition
The hold condition is what makes the SR latch useful as memory. When S = 0 and R = 0, neither input forces a change. Instead, the latch output is maintained by the feedback loop.
For example, assume Q is already 1. Since Q feeds back into the opposite NOR gate, it helps keep Q̅ at 0. That 0 then feeds back and supports Q staying at 1. The circuit therefore remains stable without needing a clock signal.
This is why an SR latch is classified as an asynchronous sequential circuit. It responds immediately, subject to gate delay, whenever its inputs change.
Basic Timing Diagram
A timing diagram shows how the latch output changes as inputs vary over time. The diagram below represents the behavior of a NOR based SR latch. The output Q changes after a small propagation delay, not instantly.
Time → t0 t1 t2 t3 t4 t5 S 0 1 0 0 0 0 R 0 0 0 1 0 0 Q 0 1 1 0 0 0 Action Hold Set Hold Reset Hold Hold
At t1, S goes high while R remains low, so the latch sets and Q becomes 1. At t2, S returns to 0, but Q stays 1 because the latch is holding its state. At t3, R goes high, so the latch resets and Q becomes 0.
NAND Based SR Latch
A NAND based SR latch works similarly, but its inputs are usually active low. They are commonly written as S̅ and R̅. The bar notation indicates that a logic 0 activates the input.
The NAND latch is common in real digital circuits because NAND gates are efficient to implement in many logic families.
NAND SR Latch Truth Table
| S̅ | R̅ | Q Next | Q̅ Next | Operation |
|---|---|---|---|---|
| 1 | 1 | Q Previous | Q̅ Previous | Hold |
| 0 | 1 | 1 | 0 | Set |
| 1 | 0 | 0 | 1 | Reset |
| 0 | 0 | 1 | 1 | Invalid |
Notice that the invalid condition is different from the NOR version. For the NAND latch, the invalid input occurs when S̅ = 0 and R̅ = 0, causing both outputs to become 1.
Practical Example: Start Stop Control
A common example of an SR latch is a simple start stop control circuit. Suppose a machine has two push buttons:
- Start button: Sends a set signal
- Stop button: Sends a reset signal
When the operator presses Start, the latch sets Q to 1. This Q output can enable a relay, motor driver, or controller input. When the operator releases Start, the output remains 1 because the latch holds its state. Later, pressing Stop resets Q to 0, turning the system off.
This behavior is valuable because the operator does not need to keep holding the Start button. A short pulse is enough to change and store the circuit state.
Invalid State and Race Concerns
The invalid state is not just a theoretical issue. If both set and reset are activated together, the latch can enter a condition where Q and Q̅ are not complements. When the inputs are released, the final state may depend on which internal gate responds faster.
In practical design, engineers avoid this by using input conditioning, interlock logic, or replacing the simple latch with a clocked structure such as a flip-flop. The goal is to ensure that set and reset are never asserted at the same time unless the device specifically defines a safe priority behavior.
SR Latch Versus SR Flip Flop
An SR latch is level sensitive. It reacts as long as the inputs are active. An SR flip-flop is usually edge triggered, meaning it changes state only on a clock edge, such as a rising or falling transition.
This distinction matters in controlled digital systems. Latches are simpler and faster, but they can be harder to manage in complex timing environments. Flip-flops are preferred in synchronous systems because the clock provides a predictable update point.
Key Points to Remember
- An SR latch stores one bit of information.
- The NOR version uses active high set and reset inputs.
- The NAND version uses active low set and reset inputs.
- The hold state preserves the previous output.
- The invalid input condition must be avoided in reliable designs.
- Timing behavior is affected by real gate propagation delays.
The SR latch is simple, but it introduces several essential ideas in sequential logic: memory, feedback, timing, and invalid states. A solid understanding of this circuit makes it much easier to study D latches, JK flip-flops, registers, and complete synchronous digital systems.
